(1) Field of the Invention
The present invention relates to a driving circuit for a control electrode provided in an image forming apparatus such as a copier which forms visual image by making the developer jump by electrical force.
(2) Description of the Prior Art
Recently, as an image forming apparatus which reproduces an image signal into a visual image output on a recording medium such as paper etc., an image forming apparatus has been disclosed in Japanese Patent Application Laid-Open Hei 5 No. 50,647. The image forming apparatus in this disclosure forms visual images on the recording medium by making statically charged toner jump by electric force (electric field) whilst the toner's direction of jumping is controlled by a control electrode arranged in the toner transfer path.
The control electrode provided in this image forming apparatus is in a flat-plate form with a plurality of holes formed therein. Each of these holes is provided with an annular electrode therearound forming a gate for controlling the passage of toner flow. Voltages are selectively applied to each annular electrode, i.e., each gate in accordance with the image signal so as to control the distribution of the electric field. Resultantly, the toner's direction of jumping is determined and hence an image in accordance with the image signal is formed on the recording medium.
Referring now to FIGS. 1 to 6, the configuration and the operation of this image forming apparatus will be shown by exemplifying a digital copier.
The present image forming apparatus can be applied to a printing section of a printer for example, other than digital copiers and has a sectional configuration schematically shown in FIG. 1. That is, the image forming apparatus has in its center an image forming unit 1 for forming an image by making toner as the developer adhere to the recording medium. Provided on the paper input and output sides of image forming unit 1 are a paper feeder 10 for supplying paper to image forming unit 1 and a fixing unit 11 for fixing the toner image formed on the paper by image forming unit 1, with heat and pressing.
Image forming unit 1 is composed of, as detailedly shown in FIG. 2, a toner supplying section 2 and a printing section 3. Toner supplying section 2 is composed of a toner storage tank 20 for storing toner 21 as the developer, a drum-shaped toner support 22, a doctor blade 23 which regulates the thickness of the toner layer carried on the peripheral surface of toner support 22 and negatively charges the toner.
Toner 21 is of a magnetic type having a mean particle diameter of, for example, 6 .mu.m, and is electrified with static charge of e.g., -4 .mu.C to -5 .mu.C per gram by doctor blade 23. Here, the thickness of the toner layer carried on the peripheral surface of toner support 22 is regulated at 60 .mu.m. In the description of this embodiment, a configuration for negatively charged toner will be detailed, but it is also possible to configure a system which uses positively charged toner.
Here, toner support 22 is rotationally driven by an unillustrated driving means in the direction indicated by arrow A in the figure, with its surface speed set at about 80 mm/sec, for example. Toner support 22 is grounded and has unillustrated fixed magnets therein, at the position opposite doctor blade 23 and at the position opposite a control electrode 26 (which will be described later). Magnetic force from these magnets enables toner 21 to stand up in `spikes` at the areas on the peripheral surface corresponding to the positions thereof. Here, instead of magnetic force, it is also possible to configure a system which supports the toner by electric force or combination of electric and magnetic forces.
Printing section 3 includes: an opposing electrode 25 arranged facing the peripheral surface of toner support 22; a high-voltage power source 30 for supplying a high voltage to the opposing electrode; a control electrode 26 provided between toner support 22 and opposing electrode 25; a dielectric belt 24 for conveying a sheet of paper 5 toward the upper portion of opposing electrode 25; a pair of rollers 16a and 16b for driving dielectric belt 24; a charging brush 8 for charging paper 5; a charger-power source 18 for supplying a charger voltage to charging brush 8; a charge erasing brush 28 for erasing charge on paper 5; a charge erasing power source 17 for applying a charge erasing voltage to charge erasing brush 28; and a cleaner blade 19 for cleaning the surface of dielectric belt 24.
Control electrode 26 as a part of printing section 3 has a configuration with its top surface schematically shown in FIG. 3. That is, the electrode has annular electrodes 27 each encircling a hole H; this hole H and annular electrode 27 form a gate 29 as the passage for jumping toner flow. A driving signal is given from a driving circuit 31 shown in FIG. 2 to each annular electrode 27 via a feed line 28, so as to control the direction of jumping flow of the toner transferring from toner support 22 to opposing electrode 25, as will be described hereinbelow.
Control electrode 26 shown in FIG. 2 has only one gate 29 shown for convenience, but a plurality of gates 29 are arranged regularly as briefly shown in FIG. 3. In practice, gates 29 are arranged at about 2,560 sites, for example, but the number and shape are not particularly limited.
Toner support 22 is composed of a substrate of a non-magnetic material such as aluminum. Dielectric belt 24 is formed of a substrate made up of PVDF of about 75 .mu.m thick with a volume resistivity of about 10.sup.10 .quadrature..multidot.cm. Opposing electrode 25 is arranged, for example, about 1.1 mm apart from the peripheral surface of toner support 22 and has a high voltage application of e.g., about 2.3 kV from high voltage source 30 so as to form an electric field between itself and toner support 22. Rollers 16a and 16b are rotated by an unillustrated driving means so that dielectric belt 24 will run at a velocity of about 30 mm/sec. in the direction of the arrow in the figure.
Although unillustrated, the image forming apparatus shown in FIG. 2 also includes: a main controller for controlling the whole apparatus; an image processor for image processing the image data; an image memory for storage of the processed image data; and an image forming control unit for converting the image data obtained after image processing into an image signal to be given to control electrode 26.
In accordance with the image forming apparatus thus configured, in FIG. 2, whilst paper 5 is being conveyed over opposing electrode 25 at a uniform speed by dielectric belt 24, the toner (negatively charged) carried on toner support 22 jumps and statically adheres to the upper surface of the conveyed paper 5 by the action of the electric field formed between toner support 22 and opposing electrode 25.
The toner's direction of jumping is determined by the potential of each gate 29 (annular electrode 27) of control electrode 26. That is, the potential of each annular electrode 27 is controlled by driving circuit 31 based on the image signal obtained from the conversion of the aforementioned unillustrated image forming control unit. The distribution of the electric field near control electrode 26 is controlled in accordance with the driving signal given from driving circuit 31, so that the toner's direction of jumping is controlled.
When, for example, a voltage of 150 V is applied to a gate 29, this gate promotes the passage of the toner (negatively charged) therethrough. When a voltage of -200 V is applied, the gate stops the passage of toner. Each gate has a selectively pulsed driving signal given from driving circuit 31 in accordance with the image signal, whereby the passage (and the direction of jumping) of the toner flow will be controlled in accordance with the image.
The control electrode 26 exemplified in FIG. 3 has one annular electrode 27 for each gate 29 and each gate is individually supplied with a driving signal via its feed line 28. In contrast, as shown in FIG. 4, there is another type of control electrode (to be referred to as `matrix type control electrode`) which has gates 29 at crossover points between two layered strip-like electrodes 27a, rows and 27b, columns and controls the potential state of each gate 29 by the relationship between electrodes 27a and 27b. In this type, the number of signal lines (feed lines) can be reduced and the scale of its driving circuit can be downsized.
Next, the copying operation in the digital copier as the image forming apparatus thus configured will be described following a flowchart shown in FIG. 5. In the description, reference to FIGS. 1 to 4 should be made as required.
First, when with an original to be copied placed on the image pickup section (without numeral) of FIG. 1 the copy start key (not shown) is operated, the image pickup section starts to read the image from the original (Step S01). The image data picked up from the image of the original by the image pickup section is image processed in the image processing section (not shown) (Step S02) to be stored into the image memory (not shown) (Step S03). This image data is transferred to the image forming control unit (Step S04) where it is transformed into a control-electrode controlling signal (Step S05).
When the image forming control unit has obtained a predetermined amount of the control-electrode controlling signal (Step S06; YES), it controls an unillustrated driving means so as to start toner support 22 (sleeve) of image forming unit 1 rotating (Step S08) and a voltage of -200 V is applied to an unillustrated shield electrode of the control electrode shown in FIG. 3 (Step S09) and then predetermined voltages are applied to opposing electrode 25, charging brush 8 and charge erasing brush 28 shown in FIG. 2 while dielectric belt 24 starts to be moved (Sep S10).
Next, a pickup roller (without numeral) of paper feeder 10 as shown in FIG. 1 is activated (Step S11) so as to supply paper 5 to image forming unit 1 detailedly shown in FIG. 2. This paper 5 is electrified at a voltage in accordance with the differential potential between charging brush 8 and roller 16a and conveyed by dielectric belt 24 at a uniform speed above opposing electrode 25. Next, when the paper is normally fed (Step S12; YES), a driving signal is supplied to control electrode 26 (Step S14) whereby toner flow is controlled so as to perform printing (image forming) on paper 5.
Here, when the image forming control unit supplies a control electrode signal to driving circuit 31 shown in FIG. 2 at the timing synchronized with the conveyance of paper 5, driving circuit 31 gives driving signals to the gates of control electrode 26 in accordance with the control electrode signal. As a result, the electric field near the gates of control electrode 26 is controlled in accordance with the driving signal and hence the toner's direction of jumping is controlled in accordance with the image data, thus a toner image (characters) is successively formed on paper 5 which is being conveyed by dielectric belt 24. The paper with the toner image thereon is pressed whilst being heated by fixing unit 11 shown in FIG. 1 so that the toner image is fixed to paper 5. When the printing (the operation of image forming) has been completed in this way (Step S15 ;YES), the operation goes back to Step S01, for preparation of reading a next original.
As described heretofore, in accordance with an image forming apparatus of this type, since the transfer process of the toner image from the developing medium to the paper is omitted, no degradation of image which would occur during the transfer process will occur in contrast to an apparatus using a developing medium such as a photoconductive drum or dielectric drum. Further, since there is no developing medium, this configuration needs fewer number of parts thus making it possible to reduce the size and cost of the apparatus.
Although the above-described image forming apparatus is for producing monochrome images, it is possible to realize a color image forming apparatus for producing color images by providing a plurality of image forming units 1a, 1b, 1c and 1d corresponding to, for example, yellow, magenta, cyan and black, as schematically shown in FIG. 6, in place of supplying section 2 shown in FIG. 2.
Driving circuit 31 shown in FIG. 2 for supplying driving signals to control electrode 26 preferably has the characteristic that it will not generate waveform distortion when the driving signal switches. If the driving signal has any waveform distortion, it becomes impossible for control electrode 26 to precisely control toner flow transfer, thus producing degradation of the image. For this reason, a conventional driving circuit for driving the control electrode uses a push-pull configuration in which CMOS drivers each consisting of a pair of p-type and n-type MOS transistors are provided as the output drivers, in order to suppress waveform distortion of the driving signals.
When the aforementioned control electrode shown in FIG. 3 in which the driving signals are applied individually to separate gates is driven, as many output drivers of the aforementioned push-pull type driving circuit as the number of the gates are needed. Suppose, for example, that the image should have a dot density of 300 DPI (dots per inch), 2560 gates are required for A4 sized paper. Accordingly, if the output drivers for the driving circuit are composed of CMOS drivers, each of which consists of two transistors, i.e., p-type and n-type transistors, the transistors needed for constituting the output drivers amounts to 5120, a very large number of transistors.
When the number of the output drivers increases, it becomes difficult to integrate them in one LSI chip due to problems of output noise, power consumption (heat generation) and mounting into the package. Therefore, the driving means is divided into a plurality of LSIs. In general, a driving circuit is embodied with LSIs which each are mounted in a QFP (quad flat package) having 64 channels (64 output drivers). When a control electrode having 2560 gates needs to be controlled as stated above, driving circuit 31 is composed of 40 of these LSIs.
In the above way, even when the driving circuit using a push-pull configuration is composed of divided 64-channel LSIs, each LSI has 64 output drivers mounted thereon and further needs additional circuits such as shift resistors, latches etc., increasing its chip size and hence its cost. Further, since the driving circuit is composed of plural LSIs, even more parts are needed further increasing the size of the device.
As well as the driving circuit of the push-pull type, there is another configuration of a driving circuit which uses pull-up resistance. This driving circuit is composed of a high-voltage power source 185 and a low voltage power source 184, and a resistance element 183 as pull-up resistance and a transistor 188 in series connected between the two power sources. In this arrangement, the switching state of transistor 188 is controlled by an image signal controlling circuit 86 so as to selectively output one voltage of high-voltage power source 185 or low-voltage power source 184 (for example, +150 V or -200 V) to the output terminal as the driving signal level in accordance with the image signal.
In a driving circuit of this type, the transistors needed are approximately half as many as those used in a driving circuit of the aforementioned push-pull configuration, thus making it possible to reduce the circuit scale. This circuit configuration, however, is liable to cause waveform distortion since one of its driving signal output levels is defined using pull-up resistance as a passive element. It is possible to suppress waveform distortion to some degree if the current is increased by reducing the resistance value of the pull-up resistor, though the power consumption increases and hence counter measures against heat are needed, resultantly increasing the cost.
If the driving signal for driving the control electrode shows any waveform distortion, various problems occur as follows. If, for example, the potential of gate 29 of control electrode 26 shows any waveform distortion in the driving signal when the signal changes into the voltage for making toner pass, the distribution of the electric field will not change at the intended timing, causing a time lag for toner jumping. For this reason, the pulse width of the driving signal for controlling toner jumping must be set longer, this needing a longer time for creating a single dot and hence lowering the image forming speed. Conversely, if the potential of gate 29 shows a waveform distortion when the signal changes into the voltage of prohibiting toner from passing through it, a time lag occurs until the transfer of toner stops. Resultantly, the dot formed shows a tail, degrading the quality of image.
In a matrix type control electrode as shown in FIG. 4, it is impossible to totally stop toner jumping. This means leakage of toner causing background fogginess in the image. Even though dots have a high enough density, if this phenomenon occurs it is impossible to inhibit toner from adhering to the background (non-toner area). As a result, the image becomes blurred, low in contrast and low in reproducible performance of halftones, or low in color reproducibility in the case of a color image.
Further, in the case where no paper is conveyed over the opposing electrode, the toner leaked through the control electrode adheres to the opposing electrode surface. In this state if a sheet of paper is conveyed over the opposing electrode, the rearside of the paper will be stained. Further, in this case, the distribution of the potential across the opposing electrode varies due to the adhering toner, affecting the jumping path of the toner and hence making it impossible to precisely control the toner jumping.
Moreover, if the toner adheres to the interior of a gate due to waveform distortion in the driving signal, the apparent potential of the gate varies to thereby disrupt the distribution of the electric field nearby. As a result, the jumping path of the toner is perturbed, causing image failures such as partial image defect and the like.
In the conventional driving circuit of a control electrode, in order to optimally suppress its dc loss, a complementary output configuration is used which needs on its high side a high-side switch (level shifter) for turning on and off its high-voltage active element whilst suppressing d.c. loss. A capacitor, which is a passive element, is used for this purpose.
FIG. 9 is an IC diagram showing a typical complementary configuration. In this complementary IC, the source of a p-channel MOS FET 704 is connected to a high-voltage power source 51 and the source of an n-channel MOS FET 705 is connected to a low-voltage power source 52. These are selectively turned on and off so as to output a voltage from high-voltage power source 51 or low-voltage power source 52.
A p-channel MOS FET ON/OFF control signal 600 generated in the internal timing generating circuit is supplied to the gates of field effect transistors connected to a logic power source 50, namely the gates of p-channel MOS FET 700 and n-channel MOS FET 701 while their outputs are connected to the gate of a p-channel MOS FET 704 via a level shifter capacitor 300. Parallel circuitry of a resistance element 301 and a Zener diode 302 is connected to a high-voltage power source 51 and the gate of FET 704, and functions as a bias element for p-channel MOS FET 704. An n-channel MOS FET ON/OFF control signal 601 is supplied to the gates of field effect transistors, namely p-channel MOS FET 702 and n-channel MOS FET 703 while their outputs are connected to the gate of an n-channel MOS FET 705.
The driving state will be explained hereinbelow.
Now, when control signal 601 is set at the low level, p-channel MOS FET 705 is turned on so that output 500 supplies the voltage from low-voltage power source 52. In this state, control signal 600 stays at the low level while the drain output from MOS FETs 700/701 is at the high level. The absolute voltage of the gate of p-channel MOS FET 704 which is connected to the level shifter capacitor is biased by resistance element 301, being set equal to the voltage of high-voltage power source 51. As a result, the gate voltage (VGS) of p-channel MOS FET 704 becomes 0 V. Therefore, p-channel MOS FET 704 stays in the OFF state so that no short-circuit occurs between p-channel MOS FET 704 and n-channel MOS FET 705.
Next, control signal 601 is changed from HIGH to LOW at time P1 as shown in FIG. 10 so as to turn off n-channel MOS FET 705. Thereafter, at time P2, control signal 600 is changed from LOW to HIGH. At this moment, a voltage V1 arises at the gate of p-channel MOS FET 704. This voltage V1 is a voltage which is obtained by subtracting the changing voltage of the output from transistors 700/701 via level shift capacitor 300, from the voltage of high-voltage power source 51.
This generates gate-source voltage VGS of p-channel MOS FET 704, so that p-channel MOS FET 704 is turned on, outputting the voltage of high-voltage power source 51 at its output. The voltage appearing at the gate of p-channel MOS FET 704 will not be maintained for a long period of time at the same level because charging is effected via resistance element 301. This time is dependent upon resistance element 301 and level shifter capacitor 300.
Next, in order to turn off p-channel MOS FET 704, control signal 600 is changed from HIGH to LOW at time P3. At this moment, the potential difference between the gate voltage of p-channel MOS FET 704 and the voltage of the high-voltage power source is V2, and when the change of transistors 700/701 is added, the gate voltage transits from this level to a level which is greater by V3 than the voltage of the high-voltage power source. This voltage causes the Zener diode to allow forward flow of current so that the gate voltage of p-channel MOS FET 704 is reset to the voltage of high-voltage power source 51 and thus it is turned off.
Then, at time P4, control signal 600 is changed from HIGH to LOW. This activates n-channel MOS FET 705, and the voltage of the low-voltage power source appears at output 500. Thus, a driving pulse defined by the voltage of the low-voltage power source and the voltage of the high-voltage power source can be generated at output 500.
In the high-voltage power source circuit and IC, a level transforming configuration using a pull-up resistor 310 as shown in FIG. 11 has been employed to control the transistor in the high-voltage side. In this configuration, when the switching speed is attempted to be increased, the value of resistor 310 needs to be set smaller. But, this makes its dc loss greater, causing a higher degree of heat from the resistance and increasing the load on the power source, resulting in unsuitability for IC configuration. On the other hand, if the value of resistor 310 is made grater, the switching speed becomes lower. This is why the aforementioned configuration shown in FIG. 9 is generally used.
The circuit configuration shown in FIG. 9, however, needs a couple of output transistors 704 and 705 for each circuit, and to individually control these transistors further needs buffer transistors 700, 701, 702 and 703, level shifter capacitor 300, pull-up resistor 301 and Zener diode 302. Moreover, level shifter capacitor 300 is required to be resistant to high voltage and of high capacitance because this capacitance determines the driving time in combination with resistance 301.
FIG. 12 shows a configuration in which a number of ICs shown in FIG. 9 are integrated. Each high-voltage resistant capacitor 300-1 to 300-n needs a certain distance between its electrodes and the total capacitance needs a certain defined area. As a result, the chip area becomes very large. Further, a p-channel MOS FET has a greater area compared to an n-channel MOS FET. If, for example, an integrated circuit having 64 channels is configured, this configuration needs 64 capacitors and 24 output transistors, increasing its chip area and hence the cost.